1. Field of the Invention
The present disclosure generally relates to the field of integrated circuits, and, more particularly, to the manufacture of an interconnect structure requiring a sophisticated barrier and/or seed layer formed between a bulk metal and a dielectric.
2. Description of the Related Art
In a complex integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of the integrated circuits, generally, the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but one or more additional “wiring” layers are required, also referred to as metallization layers. These metallization layers generally include metal lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, wherein the metal lines and vias may also be commonly referred to as interconnect structures.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby also requiring an increase in the number of electrical inter-connections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers typically increases as the number of circuit elements per chip area becomes larger. Since the fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of many stacked metallization layers that are required, for example, for sophisticated microprocessors, semiconductor manufacturers are increasingly using a metal that allows high current densities and reduced dimensions of the interconnections. For example, copper is a metal generally considered to be a viable candidate due to its superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with other metals, such as aluminum, that have been used over the last decades. In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures due to its lack of forming volatile etch byproducts. In manufacturing metallization layers including copper, the so-called damascene technique is therefore preferably used, wherein a dielectric layer is first applied and then patterned to receive trenches and/or vias, which are subsequently filled with copper. A further major drawback of copper is its property to readily diffuse in low-k dielectric materials, silicon and silicon dioxide, and other well-established and approved dielectric materials in fabricating integrated circuits.
It is, therefore, necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid any out-diffusion of copper into the surrounding dielectric material, as copper may readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. On the other hand, the barrier material may suppress the diffusion of reactive components into the metal region. The barrier material provided between the copper and the dielectric material should exhibit, however, in addition to the required barrier characteristics, good adhesion to the dielectric material as well as to the copper and should also have as low an electrical resistance as possible so as to not unduly compromise the electrical properties of the interconnect structure. Moreover, the barrier layer may also act as a “template” for the subsequent deposition of the copper material in view of generating a desired crystalline configuration, since a certain degree of information of the texture of the barrier layer may be transferred into the copper material to obtain a desired grain size and configuration. It turns out, however, that a single material may not readily meet the requirements imposed on a desired barrier material. Hence, a mixture of materials may be frequently used to provide the desired barrier characteristics. For instance, a bi-layer comprised of tantalum and tantalum nitride is often used as a barrier material in combination with a copper damascene metallization layer. Tantalum, which effectively blocks copper atoms from diffusing into an adjacent material even when provided with an extremely thin layer thickness, however, exhibits only a poor adhesion to a plurality of dielectric materials, such as silicon dioxide based dielectrics, so that a copper interconnection including a tantalum barrier layer may suffer from reduced mechanical stability, especially during the chemical mechanical polishing of the metallization layer, which may be employed for removing excess copper and planarizing the surface for the provision of a further metallization layer. The reduced mechanical stability during the CMP process may, however, entail severe reliability concerns in view of reduced thermal and electrical conductivity of the interconnections. On the other hand, tantalum nitride exhibits excellent adhesion to silicon dioxide based dielectrics, but has very poor adhesion to copper. Consequently, in advanced integrated circuits having a copper-based metallization, typically, a barrier bi-layer of tantalum nitride/tantalum is used. The demand for a low resistance of the interconnect structure in combination with the continuous reduction of the dimensions of the circuit elements and associated therewith of the metal lines and vias the thickness of the barrier layer has to be reduced, while nevertheless providing the required barrier effect. It has been recognized that tantalum nitride provides excellent barrier characteristics even if applied with a thickness of only a few nanometers and even less. Thus, sophisticated deposition techniques have been developed for forming thin tantalum nitride layers with high conformality even in high aspect ratio openings, such as the vias of advanced metallization structures, wherein the desired surface texture with respect to the further processing may also be obtained.
Since the dimensions of the trenches and vias have currently reached a width or a diameter of approximately 0.1 μm and even less, with an aspect ratio of the vias of about 5 or more, the deposition of a barrier layer in a reliable manner on all surfaces of the vias and trenches and the subsequent filling thereof with copper substantially without voids is an extremely challenging issue in the fabrication of modern integrated circuits. Currently, the formation of a copper-based metallization layer is accomplished by patterning an appropriate dielectric layer and depositing the barrier layer, for example comprised of tantalum (Ta) and/or tantalum nitride (TaN), by advanced physical vapor deposition (PVD) techniques, such as sputter deposition. Thereafter, the copper is filled in the vias and trenches, wherein electroplating has proven to be a viable process technique, since it is capable of filling the vias and trenches with a high deposition rate, compared to CVD and PVD rates, in a so-called bottom-up regime, in which the openings are filled starting at the bottom in a substantially void-free manner. Generally, when electroplating a metal, an external electric field is applied between the surface to be plated and the plating solution. Since substrates for semiconductor production may be contacted at restricted areas, usually at the perimeter of the substrate, a conductive layer covering the substrate and the surfaces that are to receive a metal has to be provided. Although the barrier layer previously deposited over the patterned dielectric may act as a current distribution layer, it turns out, however, that, in view of crystallinity, uniformity and adhesion characteristics, preferably a so-called seed layer is to be used in the subsequent electroplating process to obtain copper trenches and vias having the required electrical and mechanical properties. The seed layer, for example comprised of copper, is typically applied by sputter deposition using substantially the same process tools as are employed for the deposition of the barrier layer, wherein these deposition techniques may provide the desired texture of the seed layer in combination with the previously deposited barrier material, thereby creating appropriate conditions for the subsequent filling in of the bulk metal.
For dimensions of 0.1 μm and less of vias in future device generations, the sputter deposition of extremely thin metal layers having a high degree of conformity as required for the barrier layer and the seed layer may become a limiting factor, since the step coverage characteristics of the above-described advanced sputter tools may not be further enhanced without significant modifications of these tools, which seems to not be a straightforward development. While the deposition of the barrier layer may be performed on the basis of other highly conformal techniques, such as atomic layer deposition (ALD), which is a well-controllable self-limiting CVD-like process, it appears that the characteristics of the seed layer may be difficult to obtain by these sophisticated techniques, while throughput may also be compromised, thereby making these techniques less attractive for the deposition of the seed material.
For dimensions of 0.1 μm and less of metal lines and vias in advanced semiconductor devices, the sputter deposition of extremely thin metal layers having a high degree of conformity as required for the barrier layer and the seed layer may represent critical process steps, since the step coverage characteristics of the above-described advanced sputter techniques may depend on the overall surface characteristics of the dielectric material, which in turn has to be patterned on the basis of highly sophisticated lithography and etch techniques. Even if other process techniques may be used in forming appropriate barrier materials or seed materials, for instance on the basis of extremely conformal deposition techniques, such as ALD, which is a well-controllable self-limiting CVD-like process, superior surface characteristics also have to be provided prior to the deposition of the barrier material and seed material. For example, deposition-related irregularities during the formation of the barrier material and the seed material may cause the creation of voids in the barrier material and possibly in the subsequently deposited copper metal, thereby deteriorating the electrical performance of the resulting interconnect structure, while also contributing to a reduced degree of reliability since premature failure of interconnect structure may be observed due to a reduced resistance against electromigration caused by voids and other interface irregularities in the barrier material and/or seed material. For this reason, great efforts are being made in appropriately preparing the surface of a patterned dielectric material prior to the deposition of the barrier material and the seed material.
On the other hand, it has been recognized that exposure of the barrier and seed material prior to actually depositing the copper bulk material may have a significant influence on the overall electrical performance of the metallization system, the reliability of the metallization system and also on the process results of process steps subsequent to the deposition of the barrier and seed material. For instance, in complex manufacturing environments as are typically encountered in semiconductor facilities for producing extremely complex semiconductor devices on the basis of mass production techniques, in sophisticated etch techniques, for instance for forming vias and trenches in the dielectric material, a plurality of surface contaminations may be generated, for instance in the form of organic etch byproducts and the like, which may require sophisticated cleaning recipes, for instance on the basis of wet chemical techniques and the like. Other possible sources of contamination may represent the dielectric material itself, which may typically contain a plurality of volatile components, which may increasingly diffuse out of the material, for instance by the corresponding openings created during the previous etch processes. These volatile components may themselves, or in combination with other components, result in inferior process conditions during the deposition of the barrier and seed materials, and may also significantly affect the sensitive material system prior to actually depositing the copper bulk material. That is, exposure to the clean room ambient after the deposition of the barrier and/or seed material may result in a more or less non-predictable interaction with the exposed surface areas, for instance by organic volatile components and the like, wherein the degree of surface modification may also depend on the queue time prior to the further deposition of the copper material. During the subsequent electrochemical deposition of the copper material, which itself represents a highly complex deposition process, typically performed on the basis of sophisticated deposition strategies and complex electrolyte baths, the deposition process may be influenced even by subtle variations of the seed material caused by the previous exposure to the manufacturing environment since, for instance, a delicate adjustment of the deposition rate in extremely narrow vias or trenches may be essential for obtaining appropriately filled metal regions. Moreover, even a subtle shift of the delicate balance of the deposition rates within tiny openings and wide openings or dielectric areas may result in an increased surface topography after completing the electrochemical deposition of the copper material, which may thus contribute to more critical process conditions during the subsequent removal of any excess material, for instance on the basis of CMP and the like.
Consequently, with the continuing shrinkage of the critical dimensions within sophisticated metallization layers, it becomes increasingly important not only to monitor the deposition processes for forming sophisticated barrier and/or seed material systems, but also to evaluate the influence of the manufacturing environment, i.e., the influence of queue time, the presence of specific contaminants and the like, on the barrier and/or seed materials prior to actually filling the vias and trenches with copper.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.